module timer_2 (
    input clk,
    input rst_n,
    input start,
    output reg end_delay_1s
);
    reg [31:0] count;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            count <= 0;
            end_delay_1s <= 0;
        end
        else if (start) begin
            if (count == 50000000) begin  // 50,000,000 为1秒钟的计数
                end_delay_1s <= 1;
                count <= 0;
            end
            else begin
                count <= count + 1;
                end_delay_1s <= 0;
            end
        end
        else begin
            end_delay_1s <= 0;
        end
    end
endmodule
